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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Features
* High Performance:
-6K fCK tCK CL tAC tAC Clock Frequency Clock Cycle CAS Latency Clock Access Time1 Clock Access Time2 166 6 133 7.5 143 7 -7K 133 7.5 CL=2 -- 5.4 -7 143 7 CL=3 -- 5.4 Units MHz ns CKs ns ns
CL=3 CL=2 CL=3 --5.4 -- 5.4 --5.4
1. Terminated load. See AC Characteristics on page 16. 2. Unterminated load. See AC Characteristics on page 16.
* Single Pulsed RAS Interface * Fully Synchronous to Positive Clock Edge * Four Banks controlled by BS0/BS1 (Bank Select)
* * * * * * * * * * * * * * *
Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8, Full page Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control (x4, x8) Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 4096 refresh cycles/64ms Random Column Address every CK (1-N Rule) Single 3.3V 0.3V Power Supply LVTTL compatible Package: 54-pin 400 mil TSOP-Type II
Description
The NT5SV16M4DT, NT5SV8M8DT, and NT5SV4M16DT are four-bank Synchronous DRAMs organized as 4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4 Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 200MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC' s advanced 64Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fourteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (BS0, BS1) are strobed with RAS. Eleven column addresses (A0-A9) plus bank select addresses and A10 are strobed with CAS. Column address A9 is dropped on the x8 device, and column addresses A8 and A9 are dropped on the x16 device. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A11, BS0, BS1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 200MHz is possible depending on burst length, CAS latency, and speed grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto Refresh (CBR) and Self Refresh operation are supported.
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Pin Assignments for Planar Components (Top View)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 VDD VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
54-pin Plastic TSOP(II) 400 mil 4Mbit x 4 I/O x 4 Bank NT5SV16M4DT 2Mbit x 8 I/O x 4 Bank NT5SV8M8DT 1Mbit x 16 I/O x 4 Bank NT5SV4M16DT
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Pin Description
CK CKE CS RAS CAS WE BS1, BS0 A0 - A11 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Bank Select Address Inputs DQ0-DQ15 DQM, LDQM, UDQM VDD VSS VDDQ VSSQ NC -- Data Input/Output Data Mask Power (+3.3V) Ground Power for DQs (+3.3V) Ground for DQs No Connection --
Input/Output Functional Description
Symbol CLK CKE CS RAS, CAS, WE BS0, BS1 Type Input Input Input Input Input Polarity Positive Edge Active High Active Low Active Low -- Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which bank is to be active. During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. Data Input/Output pins operate in the same manner as on conventional DRAMs.
A0 - A11
Input
--
DQ0 - DQ15
InputOutput
--
DQM LDQM UDQM
Input
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. Active High DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. -- -- Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity.
VDD, VSS VDDQ VSSQ
Supply Supply
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Ordering Information
Speed Grade Organization Part Number Clock Frequency@CAS Latency NT5SV16M4DT-6K 16M x 4 NT5SV16M4DT-7K NT5SV16M4DT-7 NT5SV8M8DT-6K 8M x 8 NT5SV8M8DT-7K NT5SV8M8DT-7 NT5SV4M16DT-6K 4M x 16 NT5SV4M16DT-7K NT5SV4M16DT-7 166MHz@CL3 143MHz@CL3 143MHz@CL3 166MHz@CL3 143MHz@CL3 143MHz@CL3 166MHz@CL3 143MHz@CL3 143MHz@CL3 133MHz@CL2 133MHz@CL2 100MHz@CL2 133MHz@CL2 133MHz@CL2 100MHz@CL2 133MHz@CL2 133MHz@CL2 100MHz@CL2 PC133 , PC100 3.3 V 400mil 54-PIN TSOP II Note Power Supply Package
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Block Diagram
CKE
CKE Buffer Row Decoder
Column Decoder
Column Decoder
Row Decoder
Cell Array Memory Bank 0
Cell Array Memory Bank 1
CLK
CLK Buffer
Sense Amplifiers A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 BS0 BS1 A10
Sense Amplifiers
Data Input/Output Buffers DQM
Column Decoder Cell Array Memory Bank 3 Sense Amplifiers
Address Buffers (14)
Control Signal Generator
Data Control Circuitry
DQ0
DQX
Refresh Counter
Column Address Counter
Mode Register
Column Decoder
Command Decoder
Row Decoder
Row Decoder
CS RAS CAS WE
Cell Array Memory Bank 2
Sense Amplifiers
Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3). Cell Array, per bank, for 2Mb x 8 DQ: 4096 Row x 512 Col x 8 DQ (DQ0-DQ7). Cell Array, per bank, for 1Mb x 16 DQ: 4096 Row x 256 Col x 16 DQ (DQ0-DQ15).
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Mode Register Operation (Address Input For Mode Set)
BS1
BS0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register(Mx)
Burst Type
M3 0 1 Type Sequential Interleave
Operation Mode
M13 M12 M11 M10 M9 0 0 0 0 0 0 0 0 0 1 M8 0 0 M7 0 0 Mode Normal Multiple Burst with Single Write
Burst Length
Length M2 0 0 0 M1 0 0 1 1 0 0 1 1 M0 Sequential Interleave 0 1 0 1 0 1 0 1 1 2 4 8 Reserved Reserved Reserved Full Page 1 2 4 8 Reserved Reserved Reserved Reserved
CAS Latency
M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
0 1 1 1 1
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A11, BS0, and BS1. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported, sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page(actual page length is dependent on organization: x4, x8, or x16).Full page burst operation is only posible using the sequential burst type. Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected.
Burst Length and Sequence
Burst Length 2 Starting Address (A2 A1 A0) xx0 xx1 x00 4 x01 x10 x11 000 001 010 8 011 100 101 110 111 Full Page(Note) nnn Sequential Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Cn, Cn+1, Cn+2, ..... Interleave Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Not Supported
Note: Page length is a function of I/O organization and column addressing. x4 organization (CA0-CA9); Page Length = 1024 bits x8 organization (CA0-CA8); Page Length = 512 bits x16 organization (CA0-CA7); Page Length = 256 bits
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Command Truth Table (See note 1)
CKE Function Mode Register Set Auto (CBR) Refresh Entry Self Refresh Exit Self Refresh Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto-Precharge Read Read with Auto-Precharge Burst Termination No Operation Device Deselect Clock Suspend Mode Entry Clock Suspend Mode Exit Data Write/Output Enable Data Mask/Output Disable Power Down Mode Entry Device State Idle Idle Idle Idle (SelfRefresh) See Current State Table See Current State Table Idle Active Active Active Active Active Any Any Active Active Active Active Idle/Active Any (Power Down) Previous Cycle H H H L H H H H H H H H H H H L H H H Current Cycle X H L H X X X X X X X X X X L H X X L CS L L L H L L L L L L L L L L H X X X X H L H L RAS L L L X H L L L H H H H H H X X X X X X H X H CAS L L L X H H H H L L L L H H X X X X X X H X H WE L H H X H L L H L L H H L H X X X X X X H X H DQM X X X X X X X X X X X X X X X X L H X X X X BS X BS BS BS BS BS X X X X X X X X BS0, BS1 A10 OP Code X X X L H X X X X X 2 2 2 2 2 3,8 2 A11, A11, A9-A0 Notes
Row Address L H L H X X X X X X X X Column Column Column Column X X X X X X X X
4
5
6, 7
Power Down Mode Exit
L
H
X
X
X
X
6, 7
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock.Operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. Refer to the Current State Truth Table. 2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 1,0 selects bank 1; BS0, BS1 = 0,1 selects bank 2; BS0, BS1 = 1,1 selects bank 3. 3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can' remain in t this mode longer than the Refresh period (t REF) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high. 8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Clock Enable (CKE) Truth Table
CKE Current State Previous Cycle H L L Self Refresh L L L L H L Power Down L L H H H H H All Banks Idle H H H H H L H Any State other than listed above H L L H L H H H H H L L L L L X H L H L L X H L L L L H L L L L X X X X X X X X H L L L X H L L L X X X X X X X X X H L L X X H L L X X X X X X X X X X H L X X X H L X X X X X X X Entry Self Refresh Mode Register Set Power Down Refer to operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 5 4 Refer to the Idle State section of the Current State Truth Table X X CBR Refresh Mode Register Set 4 3 3 3 4 Refer to the Idle State section of the Current State Truth Table X X X X ILLEGAL Maintain Power Down Mode 3 3 3 2 Current Cycle X H H H H H L X H CS X H L L L L X X H RAS X X H H H L X X X Command CAS X X H H L X X X X WE X X H L X X X X X BS0, BS1 X X X X X X X X X Action A11 - A0 X X X X X X X X X INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 2 1 2 2 2 2 2 Notes
OP Code
OP Code X X X X X X X X X X
1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high (see page 26). 3. The address inputs depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table.
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Current State Truth Table
Current State CS L L L L Idle L L L L H L L L L Row Active L L L L H L L L L Read L L L L H L L L L Write L L L L H
(Part 1 of 3)(See note 1)
Command Action Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst 4 8, 9 8, 9 4 8, 9 8, 9 6 4 7, 8 7, 8 5 4 4 Notes 2 2, 3
RAS CAS WE BS0,BS1 L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X BS BS BS BS X X X X BS BS BS BS X X X X BS BS BS BS X X X X BS BS BS BS X X X
A11 - A0 X X Column Column X X X
Description Mode Register Set Auto or Self Refresh Precharge Write w/o Precharge Read w/o Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect
OP Code
Row Address Bank Activate
OP Code X X Column Column X X X OP Code X X Column Column X X X OP Code X X Column Column X X X
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD) is not satisfied.
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Current State Truth Table
Current State CS L L L Read with Auto Precharge L L L L L H L L L L Write with Auto Precharge L L L L H L L L L Precharging L L L L H L L L L Row Activating L L L L H
(Part 2 of 3)(See note 1)
Command Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Row Active after tRCD No Operation; Row Active after tRCD No Operation; Row Active after tRCD 4 4, 10 4 4 4 4 4 4 4 4 4 4 4 4 4 Notes
RAS CAS WE BS0,BS1 L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X BS BS BS BS X X X X BS BS BS BS X X X X BS BS BS BS X X X X BS BS BS BS X X X
A11 - A0 X X Column Column X X X
Description Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect
OP Code
Row Address Bank Activate
OP Code X X Column Column X X X OP Code X X Column Column X X X OP Code X X Column Column X X X
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD) is not satisfied.
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NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Current State Truth Table
Current State CS L L L L Write Recovering L L L L H L L Write Recovering with Auto Precharge L L L L L L H L L L L Refreshing L L L L H L L L Mode Register Accessing L L L L L H
(Part 3 of 3)(See note 1)
Command Action ILLEGAL ILLEGAL ILLEGAL ILLEGAL Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation; Row Active after tDPL No Operation; Row Active after tDPL No Operation; Row Active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Precharge after tDPL No Operation; Precharge after tDPL No Operation; Precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation; Idle after two clock cycles No Operation; Idle after two clock cycles 4 4 4, 9 4, 9 4 4 9 9 Notes
RAS CAS WE BS0,BS1 L L L L H H H H X L L L L H H H H X L L L L H H H H X L L L L H H H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L L H H L L H H X L H L H L H L H X L H L H L H L H X L H L H L H L H X L H L H L H L H X X BS BS BS BS X X X X BS BS BS BS X X X X BS BS BS BS X X X X BS BS BS BS X X X
A11 - A0 X X Column Column X X X
Description Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Write Read Burst Termination No Operation Device Deselect
OP Code
Row Address Bank Activate
OP Code X X Column Column X X X OP Code X X Column Column X X X OP Code X X Column Column X X X
Row Address Bank Activate
Row Address Bank Activate
Row Address Bank Activate
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (t RRD) is not satisfied.
REV 1.1
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(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Absolute Maximum Ratings
Symbol VDD VDDQ VIN VOUT TA TSTG PD IOUT Parameter Power Supply Voltage Power Supply Voltage for Output Input Voltage Output Voltage Operating Temperature (ambient) Storage Temperature Power Dissipation Short Circuit Output Current Rating -0.3 to +4.6 -0.3 to +4.6 -0.3 to VDD +0.3 -0.3 to VDD +0.3 0 to +70 -55 to +125 1.0 50 Units V V V V C C W mA Notes 1 1 1 1 1 1 1 1
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (TA = 0C to 70C)
Rating Symbol VDD VDDQ VIH VIL Parameter Min. Supply Voltage Supply Voltage for Output Input High Voltage Input Low Voltage 3.0 3.0 2.0 -0.3 Typ. 3.3 3.3 -- -- Max. 3.6 3.6 VDD + 0.3 0.8 V V V V 1 1 1, 2 1, 3 Units Notes
1. All voltages referenced to V SS and V SSQ. 2. VIH (max) = VDD + 1.2V for pulse width 5ns. 3. VIL (min) = VSS - 1.2V for pulse width 5ns.
Capacitance (TA = 25C, f = 1MHz, VDD = 3.3V 0.3V)
Symbol CI CO Parameter Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM) Input Capacitance (CK) Output Capacitance (DQ0 - DQ15) Min. 2.5 2.5 4.0 Typ 3.0 2.8 4.5 Max. 3.8 3.5 6.5 Units pF pF pF
REV 1.1
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13
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM DC Electrical Characteristics (TA = 0 to +70C, VDD = 3.3V 0.3V)
Symbol II(L) IO(L) VOH VOL Parameter Input Leakage Current, any input (0.0V VIN VDD ), All Other Pins Not Under Test = 0V Output Leakage Current (DOUT is disabled, 0.0V VOUT VDDQ) Output Level (LVTTL) Output "H" Level Voltage (IOUT = -2.0mA) Output Level (LVTTL) Output "L" Level Voltage (I OUT = +2.0mA) Min. -1 -1 2.4 -- Max. +1 +1 -- 0.4 Units A A V V
DC Output Load Circuit
3.3 V 1200 Output 50pF 870 VOH (DC) = 2.4V, I OH = -2mA VOL (DC) = 0.4V, IOL = 2mA
REV 1.1
10/01
14
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Operating, Standby, and Refresh Currents
Parameter Symbol Test Condition (6ns) 1 bank operation tRC = tRC(min), t CK = min Active-Precharge command cycling without burst operation CKE VIL(max), tCK = min, CS = V IH(min) CKE VIL(max), tCK = Infinity, CS = V IH(min) CKE VIH(min), t CK = min, CS = VIH (min) CKE VIH(min), t CK = Infinity, CKE VIH(min), t CK = min, CS = VIH (min) CKE VIL(max), tCK = min, tCK = min, Read/ Write command cycling, Multiple banks active, gapless data, BL = 4 tCK = min, t RC = tRC(min) CBR command cycling CKE 0.2V (7ns) (7ns)
(TA = 0 to +70C, VDD = 3.3V 0.3V)
-6K -7K -7 Units Notes
Operating Current
ICC1
60
55
mA
1, 2, 3
Precharge Standby Current in Power Down Mode
ICC2P ICC2PS
1 1 10 5 30 9
mA mA mA mA mA mA
1 1 1, 5 1, 7 1, 5 1, 6
Precharge Standby Current in Non-Power Down Mode
ICC2N ICC2NS
No Operating Current (Active state: 4 bank)
ICC3N ICC3P
Operating Current (Burst Mode)
ICC4
75
70
mA
1, 3, 4
Auto (CBR) Refresh Current Self Refresh Current
ICC5 ICC6
120 1
110
mA mA
1 1
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the other deck. 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tCK(min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable.
REV 1.1
10/01
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(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM AC Characteristics (TA = 0 to +70C, VDD = 3.3V 0.3V)
1. An initial pause of 200s, with DQM and CKE held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between V IH and V IL (or between VIL and V IH) 3. In addition to meeting the transition rate specification, the clock and CKE must transit between V IH and VIL (or between V IL and VIH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and V IH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT = 1.0ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and V IH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B: AC measurements assume tT = 1.2ns.
.
AC Characteristics Diagrams
tT Clock tCKL tCKH VIH 1.4V VIL Output Z o = 50 50pF AC Output Load Circuit (A) Vtt = 1.4V 50
tSETUP
tHOLD 1.4V
Input
Output tAC tLZ Output 1.4V tOH Z o = 50 50pF AC Output Load Circuit (B)
REV 1.1
10/01
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(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Clock and Clock Enable Parameters
Symbol tCK3 tCK2 tAC3 (A) tAC2 (A) tAC3 (B) tAC2 (B) tCKH tCKL tCES tCEH tSB tT Parameter Clock Cycle Time, CAS Latency = 3 Clock Cycle Time, CAS Latency = 2 Clock Access Time, CAS Latency = 3 Clock Access Time, CAS Latency = 2 Clock Access Time, CAS Latency = 3 Clock Access Time, CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Clock Enable Set-up Time Clock Enable Hold Time Power down mode Entry Time Transition Time (Rise and Fall) -6K Min. 6 7.5 -- -- -- -- 2.5 2.5 1.5 0.8 0 0.5 Max. 1000 1000 -- -- 5.4 5.4 -- -- -- -- 6 10 Min. 7 7.5 -- -- -- -- 2.5 2.5 1.5 0.8 0 0.5 -7K Max. 1000 1000 -- -- 5.4 5.4 -- -- -- -- 7 10 Min. 7 10 -- -- -- -- 3 3 2 1 0 0.5 -7 Max. 1000 1000 -- -- 5.4 6 -- -- -- -- 7.5 10 Units ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2 2 Notes
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A. 2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
Common Parameters
-6K Symbol tCS tCH tAS tAH tRCD tRC tRAS tRP tRRD Parameter Min. Command Setup Time Command Hold Time Address and Bank Select Set-up Time Address and Bank Select Hold Time RAS to CAS Delay Bank Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time 1.5 0.8 1.5 0.8 15 48 36 15 12 Max. -- -- -- -- -- -- 100K -- -- Min. 1.5 0.8 1.5 0.8 15 52 37 15 14 Max. -- -- -- -- -- -- 100K -- -- Min. 1.5 0.8 1.5 0.8 20 63 42 20 14 Max. -- -- -- -- -- -- 100K -- -- ns ns ns ns ns ns ns ns ns 1 1 1 1 1 -7K -7 Units Notes
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
-6K Symbol tRSC Parameter Min. Mode Register Set Cycle Time 12 Max. -- Min. 14 Max. -- Min. 14 Max. -- ns -7K -7 Units
REV 1.1
10/01
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(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Read Cycle
-6K Symbol Parameter Min. tOH tLZ tHZ3 tHZ2 tDQZ 1. 2. 3. 4. Data Out Hold Time 3 Data Out to Low Impedance Time Data Out to High Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 2.7 2.7 2 -- -- 5.4 5.4 -- 3 0 2.7 2.7 2 -- -- 5.4 5.4 -- 3 0 2.7 3 2 -- -- 5.4 6 -- ns ns ns ns CK 3 3 2, 4 Max. -- Min. -- Max. -- Min. -- Max. -- ns 1 -7K -7 Units Notes
AC Output Load Circuit A. AC Output Load Circuit B. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Data Out Hold Time with no load must meet 1.8ns (-5K, -7K, -75B).
Refresh Cycle
-6K Symbol tREF tSREX Refresh Period Self Refresh Exit Time Parameter Min. -- 10 Max. 64 -- Min. -- 10 Max. 64 -- Min. -- 10 Max. 64 -- ms ns 1 -7K -7 Units Notes
1. 4096 auto refresh cycles.
Write Cycle
-6K Symbol tDS tDH tDPL tWR tDAL3 tDAL2 tDQW Parameter Min. Data In Set-up Time Data In Hold Time Data input to Precharge Write Recovery Time Data In to Active Delay CAS Latency = 3 Data In to Active Delay CAS Latency = 2 DQM Write Mask Latency 1.5 0.8 12 12 5 4 0 Max. -- -- -- -- -- -- -- Min. 1.5 0.8 14 14 5 4 0 Max. -- -- -- -- -- -- -- Min. 1.5 0.8 14 14 5 4 Max. -- -- -- -- -- -- -- ns ns ns ns CK CK CK -7K -7 Units
REV 1.1
10/01
18
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Clock Frequency and Latency
Symbol fCK tCK tAA tRP tRCD tRC tRAS tDPL tDAL tRRD tWL tDQW tDQZ tCSL Parameter Clock Frequency Clock Cycle Time CAS Latency Precharge Time RAS to CAS Delay Bank Cycle Time Minimum Bank Active Time Data In to Precharge Data In to Active/Refresh Bank to Bank Delay Time Write Latency DQM Write Mask Latency DQM Data Disable Latency Clock Suspend Latency 166 6 3 3 3 9 6 2 5 2 0 0 2 1 -6K 133 7.5 2 2 2 7 5 2 4 2 0 0 2 1 143 7 3 3 3 9 6 2 5 2 0 0 2 1 -7K 133 7.5 2 2 2 7 5 2 4 2 0 0 2 1 143 7 3 3 3 9 6 2 5 2 0 0 2 1 -7 100 10 2 2 2 7 5 2 4 2 0 0 2 1 Units MHz ns CK CK CK CK CK CK CK CK CK CK CK CK
REV 1.1
10/01
19
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Package Dimensions (400mil; 54 lead; Thin Small Outline Package)
22.22 0.13
Detail A
10.16 0.13 Lead #1
11.76 0.20 Seating Plane 0.10
0.80 Basic
0.35
+ 0.10 - 0.05
0.71REF
Detail A
1.20 Max 0.25 Basic Gage Plane
0.5 0.05 Min
0.1
REV 1.1
10/01
20
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5SV16M4DT NT5SV8M8DT NT5SV4M16DT
64Mb Synchronous DRAM Revision Log
Rev 05/01
Preliminary Changed to Revision 1.0 Removed -75B speed grade
Contents of Modification
09/01
Added -7 speed grade. Removed Icc6 low power product grade. Changed to Revision 1.1
10/01
Changed tOH from 2.7ns to 3ns for all speed sort.
REV 1.1
10/01
21
(c) NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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